Power consumption management is now a common feature in all computing platforms, from mobile devices to servers. One feature commonly used in managing power consumption is that of dynamic voltage and frequency scaling. Many modern processors support this to allow better control over power management.
Particularly, since power—as consumed—is proportional to V2f, it is the case that by reducing voltage, significant savings in power consumption can be achieved. However, voltage reduction for this purpose sometimes requires a reduction in frequency.
Typically, this is reflected in a table of states in which processors run. For example, central processing units (CPUs) manufactured by Intel which support Speedstep® technology have a number of p-states each defining a voltage and frequency. P-states tend to be labeled with numbers in ascending order in an inversely proportional relationship to the speed of the clock frequency; thus a lower-numbered p-state should be understood herein as high p-state and relating to faster clock frequencies while a higher-numbered p-state should be understood herein as relating to low p-state relating to slower clock frequencies. The CPUs can run at any of these defined p-states. A common method for deciding on the p-state for running the CPU is to look at the utilization of the CPU. If the CPU is relatively lightly utilized, such a method lowers the p-state even though it means reducing the CPU frequency; the lowering of the p-state, indeed, will have less effect on the overall throughput. The other common methods for deciding on p-states include policy-driven setting of p-states (e.g., due to a “conserve power” mode set by a systems management software) and an application software program determining p-states based on its computing requirements. These methods reduce energy consumption in the system.
Another power management feature, of course, involves the capability of data centers to budget or limit power consumption. This is often done using clock throttling (since it is faster than p-state change). However, clock throttling presents a limited ability to reduce power consumption; it does so linearly, as opposed to quadratically (more appropriate for voltage scaling). Thus, it becomes necessary to use p-state changes to implement low power caps.
Recently developed systems have sophisticated power sensors to monitor power consumption, and these sensors are accessible from the service processors (system management processors) of the system. If one is actually to implement both power capping and a frequency governor (utilization-based, application driven or any other frequency governor as described above), the most straightforward approach would be to have a common entity (i.e., service processors) implement both so that the p-states are controlled by one entity. However, on some platforms, the p-state change can be undertaken only by the host processor itself, such that the service processors therefore must use costly interrupt mechanisms like Systems Management Interrupts (SMIs) to change the power state in the host processors. Long running SMIs increase the latency of the user programs since SMI handlers are outside the purview of the OS and are non-preemptible. SMIs also stall all CPUs in the system, thereby making it very intrusive and expensive.
Accordingly, a compelling need has been recognized in connection with providing methods and arrangements for providing both power capping and frequency governor-based power savings in a workable and efficient manner.